An integrated memory, for instance, in the form of a DRAM (Dynamic Random Access Memory) generally has a memory cell array, which includes word lines and bit lines. The memory cells are arranged at crossover points of the word lines and bit lines. The memory cells usually used in integrated dynamic random access memories have a storage capacitance and a selection transistor. The storage capacitances of the memory cells are connected via the selection transistor to one of the bit lines, via which a data signal is read out or written in. The control input of the selection transistor is connected to one of the word lines.
During a memory access, firstly a word line is activated. As a result, the memory cells arranged along a word line are in each case conductively connected to a bit line via the respective selection transistor. In this case, the stored charge is divided up in accordance with the memory cell capacitance and bit line capacitance. In accordance with the ratio of these two capacitances (i.e., a transfer ratio), this leads to a deflection of the bit line voltage. The sense amplifier situated at one end of the bit line compares this voltage with the constant voltage on the associated complementary bit line and amplifies the relatively low potential difference between the bit line and the complementary bit line until the bit line has reached the full signal level for a stored logic 1, which, for example, corresponds to a positive supply potential, or the signal level for a logic 0, which for example corresponds to a reference potential. The inverse signal levels are reached at the same time on the associated complementary bit line.
In order to achieve an arrangement of the memory cell array that is as compact as possible, generally the longest possible bit lines are sought. However, this leads to correspondingly high bit line capacitances. The consequence is a reduction of the memory cell signal to be detected by the sense amplifier as a result of impairment of the transfer ratio and an increased coupling between adjacent bit lines causing disturbing crosstalk.
In order to reduce the coupling between adjacent bit lines, the bit lines of a memory are often provided with a bit line twist to minimize the bit line coupling. The bit lines of such a memory are organized in bit line pairs. The bit lines of a bit line pair cross one another at a crossing location, the bit line twist, and otherwise run parallel to one another. Having a bit line twist causes increased series resistances on the respective bit line as a result of the crossing of bit lines.
After the access to the memory cell array, the previously selected word lines are deactivated. Afterward, the bit lines are put into the precharge state as rapidly as possible, proceeding from which state a renewed memory access can be effected. For this purpose, for each bit line pair, the respective bit line and associated complementary bit line are short-circuited and additionally connected at high impedance to a supply voltage network of the memory. In order to precharge the bit lines, generally a precharge circuit is situated in the vicinity of the assigned sense amplifier at the edge of the memory cell array. The precharge circuit assigned to a bit line pair and the assigned sense amplifier are connected to the bit line pair at one end of the bit line pair at the edge of the memory cell array. The consequence is that the precharge operation of a bit line pair causes a relatively high RC constant, due to the relatively high series resistances and bit line capacitances of the long bit lines provided with a bit line twist. However, this leads to a comparatively slow precharge operation.